Study On Anti-Jimming For IF Progressing Platform Of GPS Receiver

GPS is the most widely used navigation system in the world. With the increasing of the complex electromagnetic environment, people begin to focus on the research of the anti-jamming technology for GPS receivers.There are two aspects in the anti-jamming technology for GPS receiver. On the one hand is to imrove the anti-jamming algorithm which can enable the GPS receiver to capture and track the weak GPS signal and complete the navigation solution. On the other hand is to optimize the performance of the GPS receiver handware system, increase the dynamic range of the signal which the GPS receiver receives and improve the anti-jamming performance of the GPS receiver through the rational design of the circuit and the high performance sampling programs. The paper focuses on the latter one.First of all, the paper introduces the design theory of the high-speed digital system, analyzes the effect which the sampling clock jitter on the signal to noise ratio of high-performance digital system, analyzes the conversion relationship between the sampling clock noise and the clock jitter, researches the drive circuit of the IF sampling front-end.Secondly, the paper focuses on the design method of the GPS receiver IF processing platform. It analyzes the analog channels module, sampling module, clock module, data processing module, power module. Selects the chips according to the system requirements and designs the specific circuit.Thirdly, uses the high-performance PCB design method in the hardware development and makes the important signal impedance matching through the width and the space of the line. Designs the PCB aims at minimizing the board-level noise. Tests the clock performance and the power performance of the system.Finally, studies the IF anti-jamming algorithm for GPS receiver. Implements the DLMS algorithm in FPGA device to improve the parallelism of the data processing unit. Completes digital filter design of the symmetrical structure fixed-point DLMS based on FPGA according to the simulation results.