Technology On Design And Implementation Of Pulsed Coherent Radar Digital Receiver

With the rapid development of Analog-to-Digital Converter (ADC) and Field Programmable Gate Array (FPGA), the trend of digital receiver is high intermediate frequency (IF), wide-band, high dynamic range, and high sensibility. At the same time, because the advantages in receiving and processing cost, the synthetic wide-band technologies represented by stepped frequency (SF) have gain more and more attention. These developments have brought forward new problems to the design of traditional digital receiver which is based on narrow-band bandpass sampling theory. By designing a digital receiver of a typical multi-mode radar detector, this paper studies three problems, including designing method and theory of pulsed coherent radar digital receiver, de-ghosting of inverse V-shape stepped frequency signal which influences the sensitivity, and the implementation technologies of the receiver system. This paper is arranged as follows.Chapter 1 introduces the background and significance of the problem to be studied firstly. Secondly the designing theories, applications and technologies of radar digital receiver are reviewed, and the development of digital receiver in the future is also forecasted. Finally, the key problems to be resolved in this paper are analyzed.Chapter 2 focuses on the design of digital receiver. Firstly the basic principles and performance indices of digital receivers are introduced. Then considering the close relationship between ADC and the key indices of digital receiver such as sensitivity, noise coefficient, dynamic range, an ADC index design method is proposed in association with the front-end of the radar receiver. Finally, a digital receiver of the multi-mode radar is designed employing the traditional theory and the ADC index design method proposed, and the work includes design of ADC indices and Digital Down Converters(DDC). Chapter 3 focuses on the particularity of pulsed coherent signal, the samplingconditions and the receiving methods are analyzed, which complete the designing theory of pulsed coherent digital receiver. Firstly the IF sampling conditions are discussed, the conditions to keep coherence between pulses and zero frequency offset are presented, then the influence on signal processing is analyzed when the conditions are unsatisfied. Secondly the two IF receiving methods burst receiving and pulse reveiving are compared, their equivalent conditions are obtained, and the influence on the performance IF sampling is analyzed when the conditions are unsatisfied. A selecting scheme between the two methods in pulsed coherent radar is proposed in association with the characteristic of FPGA. The conclusions are meaningful both for the design of digital IF receiver and for the selection of system parameters in pulsed coherent radar. Chapter 4 studies the de-ghosting of inverse V-shape stepped frequency signal in order to solve the sensitivity descending problem caused by ghosting. The basic concept and cause of ghosting is introduced firstly. Secondly a de-ghosting method based on correlation of range profiles is proposed, the kernel of which is velocity estimation. Finally, the principle and process flow of the algorithm is introduced, and the algorithm is validated by comparing with similar algorithm.Chapter 5 focuses on implemention and test of digital receiver. The hardware design is discussed firstly, including the selection of ADC and FPGA chips and the design of sampling clock. Secondly, in implemention of digital receiver in FPGA, the low-pass filter in Digital Down Converter (DDC) is simplified, and a filter output truncation and calibration method is proposed in cascade filters structure. Finally, the sampling performance and the whole receiving performance are tested, and the testing results validate the design methods and theories of this paper.