Research On Reconfigurable Direct RF Sampling Receiver

With the rapid development of modern electronic communication integration technology, reconfigurable digital radar receiver technology has become a hot spot in researchers both at home and abroad. The reconfigurable direct RF sampling digital receiver can receive signals from different frequencies and bandwidth by adjusting its own parameters without altering the hardware design. This may not only save the size of hardware, but also realize great flexibility and scalability by adjusting related parameters according to the feature of received signals.In this thesis, the structure of reconfigurable direct RF sampling receiver is analyzed, and differences between reconfigurable direct RF sampling receiver and conventional receiver were analyzed theoretically. Then a scheme of reconfigurable RF sampling receiver was proposed. The whole system was first simulated and analyzed using Matlab. Then the structure was realized and verified in FPGA.The primary work of this thesis includes:1. The structure of reconfigurable direct RF sampling receiver was theoretically analyzed and presented, and related theoretical foundation was also involved.2. Key technologies of reconfigurable RF sampling receiver architecture were studied. Then we analyze the influence of pulse string bandwidth and sampling clock jitter on received signals. Simulation results were also given to verify the influence in Matlab.3. The model of noise de-jittering was established for the existence of sampling clock jitter. The de-jittering was achieved in two steps. First we introduce a calibrating signal from the front end. And phase of jittered RF signal can be estimated by the known jittered phase of the calibration tone. Secondly we research de-noising algorithm of baseband signal to improve the SNR of the receiver.4. A scheme of a dual-band reconfigurable receiver was proposed. Digital signals after ADC can be down-converted to baseband using a few steps, including digital down-conversion and cascade technique of CIC filters and HB filters. Adaptive filter was also simulated in Matlab to verify the reasonableness of the receiver.5. Simulation design on FPGA was implemented. The results of Modelsim and Matlab simulation tools demonstrate the feasibility and specification request of the receiver designed.