High Precision And Time Synchronous Ethernet PCS Sub-layer Design

In today's era,Ethernet transmission has been developed rapidly,the transmission flow is increasing day by day,the transmission network is facing great pressure,at the same time,Ethernet transmission on the network time synchronization accuracy requirements are also more and more high.In order to solve this problem,this thesis has put forward the effective method based on IEEE1588v2 protocol to eliminate the timestamp jitter: FIFO waterline back pressure control method and the uniform envelopment rate characterization method,realized the function of 100 g Ethernet PCS sublayer and high precision time synchronization,and in 100 g Ethernet physical coding sublayer(PCS)structure has been optimized,physical coding sublayer were analyzed in detail the function of each module and implementation method.The main work of this thesis is as follows :(1)PCS layer design is divided into two directions: receiver and sender,mainly composed of 64B/66 B codec,add and unscramble,align word insert and delete,bit width transformation,01 head search,AM locking,channel correction and rearrangement,accurate clock synchronization and other modules.(2)Accurate clock synchronization module obtains delay information by inserting and extracting time stamp in the transmission link,and then adjusts the master-slave clock according to the delay information,so as to achieve accurate clock synchronization.(3)The design was simulated and verified by building UVM simulation platform,and the simulation results of each design module were given.The simulation results were analyzed in detail.(4)The delay data of the receiver and sender in the design are collected and analyzed in the experiment.The simulation results show that the design successfully realizes the function of PCS layer,and the proposed method to eliminate timestamp jitter can effectively eliminate timestamp jitter,and the range of timestamp jitter is within 30 ns,achieving the effect of accurate clock synchronization.