Research On Marching-on In-time Scheme And The Fast Algorithm Of Time Domain Integral Equation

As the communication technology and IC process continues developing, data processing become faster and faster, and that brings higher requirements for data transmission. Serial links occupy the leading position in the high-speed communication for its low crosstalk and simple structure. So SerDes interface circuit become a vital module in modern communication. And the power consumption of typical SerDes in recent years were about 10mW/Gbps, it’s unaffordable for hundreds of gigabits or even terabits high-speed transmission. And in some special applications, such as mobile terminals, high power consumption SerDes interface is unacceptable. Therefore, low power SerDes design has become an important research topic.SerDes interface circuit includes a transmitter, receiver and clock module. Its low power design need to achieve relatively high data rate and reduce power consumption as much as possible. It’s also need to maintain signal integrity, minimize waveform distortions in high-speed transmission caused by non-ideal factors of transmission lines. And transmitter design is one very important aspect for its relative high power consumption. Besides data rates and power consumption, in order to maintain signal integrity, the design of transmitter need to reduce the jitter of clock and data, use differential output to reduce electromagnetic interference and crosstalk, and match impedance to reduce reflection.After study the theory of noise and signal integrity in high-speed transmission, this paper determined the design specifications based on analysis of SerDes transmitter power consumption and associated protocol. And then we designed a SerDes transmitter with a LVDS driver. In order to reduce power consumption as much as possible, serializer adopted a tree structure based on clock inverter, and serialized 8-bit parallel data into one differential signal. And the first two stage MUX use single-ended signals just transferred it before the last MUX. The serializer uses a half-bit-rate clock and its highest frequency is 2 GHz. The clocks generated by a series of frequency dividers, and the dividers output four-phase clocks in order to meet the timing requirements of data and clock. The driver uses a LVDS structure and work at 0.3 V, the voltage supplied by a regulator. An N-over-N structure was used to meet the needs of the circuits working at low voltage; it can also bring lower power consumption and less parasitic capacitors. An impedance control circuit was adopted to ensure the impedances of driver and transmission cable are matched, and it can minimize reflections.This design use SMIC 0.13μm process, the entire circuits operate at 0.8V, simulation results show that the highest data rate is 4Gbps, differential output swing is 300 mV, overall power consumption of the entire circuits is 3.54 mV, power efficiency is 0.89mV/Gbps. And other specifications, such as signal rise and fall time, undershoot, impedance match, all meet the requirements of LVDS protocols.