Research Into Impact Of NBTI Effect On Digital Combinational Logic Circuit

IC process has entered deep nanometer scale, higher demand of reliability is requested when designing digital circuit. Negative bias temperature instability (NBTI) effect under low electric field has become a typical analytical focus affecting IC performance. Being under negative bias stress for a long time, logical circuit will suffer more than 10% of shift in threshold voltage, thus causing increase in circuit delay. Conducting research into NBTI effect in digital circuit is really critical.This paper gives a complete analysis on NBTI effect in combinational and sequential logic circuit based on gate-level NBTI reaction-diffusion model. Systematic prediction of circuit delay considering NBTI effect is also presented. Main achievements are listed as follow:1. Calculate device threshold voltage shift based on gate-level NBTI model. Carry out simulation and data fitting for each kind of logic gate in digital combinational circuit to calculate delay degradation.2. Offer calculation method for delay degradation in digital logic path. Analyze NBTI-considered delay degradation in paths consisted of gate series.3. Design circuit structure analyzer according to circuit description in Verilog netlist. NBTI calculator is proposed and showed in the form of user interface to give a whole analysis of path interpretation, NBTI degradation calculation, critical path detection and maximum delay calculation.4. Carry out simulation and data fitting for D Flip-Flop. Analyze NBTI effect on circuit delay degradation in sequential circuit. Present systematic solution to calculate NBTI delay degradation in sequential circuit.