Design Of Fractional-N Frequency Synthesizer With Constant Bandwidth For UHF RFID Reader

UHF RFID technology has been widely used in logistic and traffic management because of its many advantages, such as long identification distance, small form fact and non-contact. The frequency synthesizer is an important module in a UHF RFID reader. This paper aims to design a fractional-N frequency synthesizer with constant bandwidth and low phase noise, which can support multiple protocols of the UHF RFID. The main work is as follows:1. Based on the requirement of EPC C1G2 protocol, ETSI 302 208-1 local regulation and Chi800/90MHz RFID draft, the parameters of the frequency synthesizer have been determined.2. To meet the stringent requirement of UHF RFID reader for LO phase noise, a fractional-N frequency synthesizer with constant bandwidth has been designed by realizing a VCO with constant tuning-gain KVCo. The digital-controlled capacitor array units (DCCA) and digital-controlled varactor array units (DCVA) has been used in VCO and achieved constant tuning-gain and uniform sub-band interval. In addition, an optimized calculation method is proposed to attain the accurate capacitor ratio for DCCA and achieved a tuning gain with ±6% variation and a sub-band interval with ±8% variation.3. In terms of the long settling time and residual fractional error existing in counting-based AFC technique. A division-ratio-based AFC technique has been used in fractional-N frequency synthesizer and residual fractional error can be eliminated. Meanwhile, the settling time of AFC has been greatly shorted to 3.3μs by counting the signal of VCO divided-by-2.4. For method with the non-ideal characteristics of the conventional charge pump (CP), bootstrap charge pump is used. And the dynamic current mismatch is less than 1%. A MASH 1-1-1 DSM has been realized by digital process and realized the decimal division.5. A fractional-N frequency synthesizer compliant with multiple protocols for UHF RFID reader has been implemented in 0.18μm CMOS process. The supply voltage is 3.3 V except the NPS n DSM and AFC use 1.8V supply. The whole power consumption is:28mA@3.3 V,8mA@ 1.8V. Post simulation illustrates that the output frequency of VCO range from 3.21-4.02GHz, the settling time of frequency synthesizer is about 30us (ε=10-5) and the reference spur is about-60dBc. Matlab simulation indicate that the range of loop bandwidth is 87.2-92.3kHz (±3%) across 840-960MHz output frequency and the worst output phase noise of the frequency synthesizer is 109dBc/Hz@200kHz,-129.2dBc/Hz@1MHz.