Design Of Universal Switched Capacitor Filter With Adjustable Center Frequency

In this paper,a general switched capacitor filter is designed.Firstly,this paper introduces the development of switched capacitor filter and the research results at home and abroad in recent years.Then the working principle of equivalent resistance of switched capacitor is analyzed,and the structure of switched capacitor integrator sensitive to parasitic capacitance and that insensitive to parasitic capacitance are compared.The standard response of second-order filter is analyzed in detail,and the non ideal factors of switched capacitor filter are discussed.Combined with the design requirements,the appropriate filter structure is selected to complete the system level modeling of the filter.Through the use of ideal components in cadence to build the whole filter system,and the simulation verification of the ideal system,we can get the design indicators such as clock center frequency ratio,offset voltage,Q value accuracy and its temperature coefficient to meet the requirements.After the system level verification,we design the whole system at the circuit level,Through the use of 0.35 um BCD high-voltage 24 V process to build each circuit sub module,including low output impedance amplifier design,two-phase non overlapping clock design,transmission gate switch design,charge pump and clock boost circuit design,reference current circuit design,which focuses on the charge injection of the switch caused by the DC offset are carefully analyzed,Finally,a complete general-purpose switched capacitor filter is built through these circuit sub modules,and the whole filter is simulated and verified.The results show that the filter can output low-pass,band-pass and band stop responses at the maximum 3MHz clock,the clock center frequency ratio is 24.957,the Q value is 5.0111,the output DC offset is8 m V,and the power supply current is 8m A,The temperature coefficients of Q and fo are0.83 ppm /? and 0.875 ppm/?.Meet the requirements of design index.Finally,according to the circuit,the layout design is carried out,the layout area is2200um×2800um,and the layout is verified by simulation.The verification results show that the frequency ratio of the clock center of the filter is 25.09,the Q value is 5.04968,the maximum operating frequency is 3MHz,the DC offset voltage is 5m V,the power current is 8m A,the Q temperature coefficient is 2.5ppm/ ?.The fo temperature coefficient is 0.92ppm/?,meet the design requirements.