Design Of Ultra High Speed Image Acquisition System Based On FPGA

Ultra high-speed image acquisition and transmission system is generally refers to the image acquisition speed greater than 100 frames/s, single frame image resolution is greater than 10 million pixels high speed image system, this system widely used in military image processing, micro vision, high-speed on-line detection and other fields. In order to realize the high resolution, super high speed image can be quickly and real-time into the image acquisition system, the current general use of the way is to design a special PCIe image acquisition board. However, such systems have the defects of large volume, low real-time performance, large power consumption and so on.Therefore, this thesis proposes a design based on FPGA processor for the ultra high speed image acquisition system. In the selection of hardware interface image access, the system uses camera link high-speed image acquisition interface to achieve ultra high speed data acquisition and transmission of the image; in the FPGA and chip and other interface selection, the system adopts Xilinx Kintex-7 series of high-end FPGA chip, two pieces of 128 MB of DDR3 chips, rapid I/O high-speed transmission channel, to ensure that the data throughput of the system.The main work of this thesis is mainly reflected in the following three aspects:(1) Schematic diagram, PCB diagram design, through the study of Xilinx company to provide the official information and manuals, complete schematic design and PCB design.(2) EMI design, through the PCB board diagram of the simulation test and analysis, and then to optimize the design, and ultimately make the PCB board has a good electromagnetic compatibility.(3) FPGA image acquisition software system design, logic to achieve Link Camera protocol and image acquisition. This can save hardware resource and cost and reduce the difficulty and space layout. Can also be in without changing any hardware under the premise, with the software flexible conversion base, medium and full in three modes; DDR3 register. The HD image transmission, the connected with large capacity storage is required; SRIO high-speed transmission channel, the high-speed channel is image data from the acquisition terminal (FPGA) to end processing (DSP) bridge.Finally, through the actual project designed for ultra high speed image acquisition and transmission system was validated results show that the system can to 90 frames per second, the speed of transmission of image data, single frame image resolution of 1280x1024, basically reached the performance requirements of 100 frames per second.