Design Of A Self-aware Dynamic Power Management Module For SoC

Along with the rapid development of integrated circuits (IC) design technology and the continuous improvement of IC manufacturing process, the performance requirement of embedded products increases a lot and the design of SoC chips becomes more and more complicated. Because of these, the power consumption of a SoC system keeps increasing nowadays. At the same time, there is no breakthrough in battery energy storage technology, which makes low power design a very significant part in a SoC design process.This thesis firstly introduces the sources and theories of power dissipation in CMOS integrated circuits including switching power, short circuit power and leakage power, and then analyses the low power design methods to reduce these kinds of power consumption in principle, using a CMOS invertor as an example. Secondly, this thesis makes a further study about the most popular low power design methods in SoC design including Dynamic Voltage and Frequency Scaling (DVFS), Clock Gating, Power Gating and Dynamic Power Management (DPM).On this basis, this thesis proposes a self-aware dynamic power management system, which is able to adjust the working states of different modules in the SoC by using multiple low power design methods to reduce the power consumption within the performance being satisfied, according to the usage of the resources in SoC by the feedback of the hardware monitor system and pre-configured working point transforming strategy. Afterwards this DPM system is designed and implemented based on the CK802 High-Energy-Efficiency SoC Platform of Hangzhou C-SKY Microsystem Co. The implementation mainly includes the power domain dividing of the SoC platform, several low power modes for the SoC system and the detailed design of every part of the DPM system like power management unit and monitor unit.At last, this thesis conducts some simulation for the implemented DPM system based on the CK802 High-Energy-Efficiency SoC Platform. According to the testing result of a 2048-bit deciphering application, a proper working point configuration is able to reduce 42% power consumption with almost the same performance by using the DPM system to gate off the clocks and power of the idle modules. Besides, the minimum standby power consumption in the low power mode is as low as 0.002mW under the SMIC55 process. What’s more, the area of the implemented DPM system is accounted only 3.5% of the whole area of the SoC system.