Research-Oriented Customizable System-On-Chip Platform On FPGA

Researches in Computer Architecture sometimes are very difficult, due to lack of visualization, poor debugging methods and high tape-out cost. Then there appears cycle-accurate full system simulators like Gem5, and FPGA, a kind of programmable circuit structure, which brings a new dawn.This thesis describes a small but complete System-On-Chip (SOC) design implemented on FPGA, which is modular, customizable, easy to port, and highly scalable. As a fundamental research platform, this design is ideally suited for rapid prototyping and verification in various architecture research areas.The main works of this thesis are:1. Design and implement a 5-stage pipeline CPU, which is compatible with MIPS ISA and supports 53 commonly used instructions.2. Design and implement a set of core modules, including CPO, Cache, MMU, and interrupt controller, meeting the requirements of multi-task operating system.3. Design and implement the internal bus communication system to connect CPU and external devices, supporting Wishbone interface and burst transfer mode.4. Design and implement necessary device modules, including PS2, UART, VGA, FLASH, PCM and SD card, which are managed with a reasonable address mapping strategy.5. Combine all components above to constitute a small but complete SOC system, which can be run independently, while ensuring low coupling among modules. All modules can be configured conveniently, including MMU, Cache and other core components.