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Design Of Network On Chip Hardware Simulation Test Platform Based On FPGA

Posted on:2024-04-24Degree:MasterType:Thesis
Country:ChinaCandidate:Y ShanFull Text:PDF
GTID:2568307097457974Subject:Electronic information
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With the rapid development of microelectronics technology,on-chip networks have become an effective solution to global communication problems in large-scale integrated circuit design due to their high throughput and good scalability.Researchers use software and hardware to model and simulate on-chip networks,while hardware testing platforms can more efficiently test on-chip networks and test them closer to actual circuits.The testing platform based on FPGA design can better conduct network on chip simulation testing due to its flexibility and low cost.After analyzing the structure and working principle of on-chip networks,this article first designs a relatively universal packet format that can adapt to most on-chip networks.When the network under test requires a special packet format,the parameters can be modified as needed.Build a flexible and configurable hardware testing platform based on the basic structure of the on-chip network.The LFSR algorithm is used in the data packet generation module to generate universal,large,and random coverage tests.The data generated by the algorithm is used as the data for the data packets,and the algorithm and set parameters are used to generate information such as destination address,packet length,and interval between data packets.The monitoring module uses the timestamp information of data packets to count and calculate latency at the receiving node to complete network performance testing.The monitoring module uses the timestamp information of data packets to count and calculate latency at the receiving node to complete network performance testing.Using FPGA’s AXI Generator and AXI Monitor as advanced modes for data generation and monitoring modules,this mode can be used to generate special format data and calculate information such as write transfer count,write delay time,and total number of bytes written.By using Vivado’s testing platform for the network to be tested and a testing platform without the network to be tested,the power consumption is calculated after analysis.This article tested three Ring type networks and one Torus type network,and the test results showed that the testing platform designed in this article can complete simulation testing on different networks.The testing platform built in this article is flexible and configurable,capable of meeting various topologies,automatically generating random data packets with different injection rates,and automatically completing the collection of network testing data.It can quickly simulate and test different networks.
Keywords/Search Tags:Network On Chip, Testing platform, FPGA, Testing
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