Research On Key Technologies Of Hardware/Software Collaborative Computing Based On Reconfigurable Mechanism

As FPGA scale gradually increasing, hardware design is becoming more and more complex, and the programming difficulty and workload are also greatly increased. Compared with traditional HDL programming, high-level synthesis possesses a higher level of automation. It can reduce design difficulty, shorten development cycles and improve working efficiency. The continuous development and improvement of high-level synthesis will promote the reconfigurable computing towards truly practical. Therefore, high-level synthesis is getting more and more attention of researchers.This thesis focuses on solving the HW/SW collaborative computing problems in reconfigurable systems with the method of high-level synthesis. Its major research contents and innovation including:1. After intensive study on implementations of high-level synthesis, a hardware and software collaborative method, named of CSPE, is proposed for applying the high-level synthesis tools to loosely coupled reconfigurable computers. CSPE has been implemented on the PRCA prototype platform created by our research group. The intended programming target of most existing high-level synthesis tools are systems on programmable chips, in which the generated software programs are executed by embedded processors. Researches on system level synthesis are just starting, and there are no mature universal tools yet. The CSPE method proposed by this thesis makes slightly changes to the existing high-level synthesis tools, and then they are able to be applied to loosely coupled reconfigurable systems, thus expanding the application scope of these tools.2. Based on existing reliable transport protocols on data link layer, a sender-dependent asymmetric protocol ARTP is designed, and the hardware interface module in accordance with this protocol is also implemented. The resources on FPGAs are limited, and the control logic should not be too complex. ARTP provides that the Get-back-N protocol should be used when general processors send data, and Stop-and-wait protocol used when FPGAs send. Thus the buffers on the FPGAs can be minimized, and the complexity of control logic can be lowered. Both theoretical analysis and experimental verification proves the validity and reliability of this protocol.3. A parallel processes execution method based on Impulse C named as WSFR is presented, which improves the execution efficiency. This thesis does an in-deep study on the working mechanism and characteristics of Impulse C, which is a typical mature high-level synthesis tool. For its weakness in the parallel processes execution, WSFR method is proposed, which increases the width of the stream to improve the execution efficiency of hardware.4. Based on the direct memory access mode of Impulse C, a bus bridge named as EWBB is designed and implemented. EWBB connects the mem interface of Impulse C with the UI interface of MIG, accessing the memory directly, not relying on any universal bus. In order to maximize reading efficiency, this bus bridge supports a rapid reading mode for the working style of Impulse C. In this mode, reading each datum into an array on the chip consumes only about one clock cycle.Finally, applications such as N-body solving program have been developed in the customized high-level synthesis environment, as experimental examples to simulate and verify the methods proposed above, and the experimental results have verified the correctness and effectiveness of the work.