Design Of A High Linearity Low Jitter Voltage-Controlled Oscillator

More and more attention is being attached to the research and exploitation of radio frequency (RF) and wireless transceiver as the rapid development of mobile communication technology. As an important part of clock data generation and recovery circuit, phase locked loop (PLL) is widely used in RF and wireless communication circuits, whose frequency is mainly produced by the voltage-controlled oscillator (VCO). In recent years, the continuous promotion of CMOS technology makes system on chip (SOC) possible, however, it also brings challenges to VCO, for example, the VCO gain changes with the variation of input voltage and the output signal is influenced by the power fluctuation in high frequency environment and so on.There are many kinds of VCO, different types of oscillators should be chosen according to different application requirements. In the field of radio communication and broadcasting, the required frequency of PLL synthesis is tens of megahertz to several hundred megahertz. So the study of VCO in our paper should be focused on high linearity and low jitter. Firstly, an appropriate type of VCO is selected and a basic structure of oscillation circuit is proposed in the paper. Secondly, according to the wanted result, the VCO circuit is divided into several modules and each module is designed to fulfill the required functions. Thirdly, modules are put together for the overall simulation and further optimization. Finally, the layout of the circuit is designed. The innovation points of the paper are listed below.A voltage to current converter is designed with high linearity which can reduce the influence of output current caused by the power fluctuation through the feedback loop within itself. Compared with the conventional type, our design has a more widely tunable range and less power consumption under the circumstance of high linearity. A high power supply rejection ratio (PSRR) and zero temperature coefficient regulator is designed as the internal power supply which can reduce the influence of output signal caused by the power offset and temperature variation. A self-biased cascade circuit with two resistors instead of conventional biased structure is used as bandgap reference, reducing the voltage consumed by the reference as well as the power dissipation. A kind of self-starting circuit is designed to avoid the unwanted zero biased point. A current-controlled oscillator circuit with simple structure is designed which can generate a triangle wave through the reversal charge and discharge to the grounded capacitor controlled by a charge pump with pass transistor switches. A buffer circuit is designed to transfer the triangle wave to a square wave. The design has less power consumption and smaller chip size resulting from the nonexistence of resistors or inductors integrated in the oscillation circuit.A high linearity low jitter VCO based on 0.7μm DPTM 3.3V CMOS process technology and simulated based on Cadence software is proposed in the paper. The required specifications for the proposed VCO are:linearity (less than 10%), period jitter located on the central frequency(less than 0.05ns) and overall power dissipation (less than 5mW).