The Design And Implementation Of A Dual-Channel SDRAM Storage Control Module

With the wide use of multi-mode multi-band radio frequency integrated circuits (RFIC), the RFIC chip test has become the focus of people’s attention. However, the simultaneous test of multiple receiver channels of a multi-mode multi-frequency RFIC depends on a multi-channel, high-speed, serial storage module. Therefore, it’s of high importance to design a multi-channel SDRAM data storage control module for the test of RFICs based on FPGA.The purpose of this paper is to design a dual channel SDRAM data storage control module, adaptive to the sampling rates of the front-end analog to digital converter (ADC) in the range of 26MHz to 61.44MHz to realize the storage of two continuous, parallel baseband data with the maximum data flow rate of 61.44MHz × 28b, facilitating subsequent data processing and analysis output from the RFIC. Firstly, this paper adopts a buffer solution based on asynchronous FIFO to solve the two main problems existing in the stored procedure:the problem that a SDRAM chip cannot meet the requirement of a real-time continuous data stream storage and the problem that the data stream rate and memory rate are asynchronous. Secondly, this paper has accordingly made two aspects of optimization and improvement:firstly, in order to solve the two-way data sharing SDRAM memory problem, this paper designs a scheduling algorithm based on weighted round robin(WRR) arbitration module to ensure the bandwidth requirements of the dual-channel datas; and secondly, in order to save resources this paper has reduced the asynchronous FIFO depth with the assurance of the effective data transfer bandwidth utilization.Finally, this paper builds a verification platform, composed of a FPGA development board for RFIC automated test, a AD acquisition board, a logic analyzer of Agilent 16902B, a DC voltage source of Agilent E3631A, a waveform generator of Agilent 33500B, a vector signal generator of E4438C and a PC to validate the research results. The results shows that the storage control solution can achieve a storage of two consecutive parallel data stream at 64.285713MHz, in the case of the SDRAM of MT48LC32M16A2’s voltage at 3.3V, frequency at 133MHz, asynchronous FIFO depth at only 16 words, namely the effective data transfer bandwidth utilization to reach 96.67%.