Research On Low-power Technology In Back-end Design Of A Voice Chip Based On 28nm Manufacturing Process

In recent years,integrated circuits have been developed rapidly following Moore's Law.IC technology,design,and EDA tools have also continued to grow.The process of integrated circuits is becoming more and more advanced and with the continuous improvement of integration,a compromise between area and performance is needed in the design of the chip.The importance of power consumption in portable devices has gradually emerged.The excessive IR Drop on the chip's power supply network will increase the delay of the standard cell and the delay will make the timing more difficult to converge,or even make the function of the chip invalid.Therefore,the problems of IR drop violation and low-power technology realization must be solved by digital circuit back-end designers.This thesis conducts research on low-power physical design based on the placement and routing tool Innovus launched by Cadence.In response to a 28 nm AI voice chip's extremely important requirement for power consumption,the low-power physical design of this chip is realized by using CPF.In order to meet the low-power requirement of the chip,some power domains need to be able to independently complete the shutdown process when idle.Therefore,the chip is divided into six Power Domains and the Power Shut Off technology is used to achieve the requirement of reducing the static power consumption of the chip.The design aims to better implementation of Power Shut Off technology to reduce static power consumption of this chip.Meanwhile the physical design of the chip is completed and the IR Drop sign-off requirements is met.According to the theory of Power Shut Off technology,the selection of the Power Switch will affect the rush current in the power-up simulation.In the back-end design process,it is necessary to solve the trade-off between the increase in IR drop caused by the rush current and the wake-up time required by the design.In order to solve the above problems,the thesis proposes a calculation model basis on Daisy Chain which establishes the calculation relationship between time and rush current or transient voltage.This calculation model can be used to simulate the power-up process of the Power Domain which have Power Switch in the circuit in advance,so as to prevent large rush current.Finally,the influence of different types of power switches on the rush current is analyzed and compared.After the Power Shut Off technology is implemented in this project,the simulation result shows that the static power is roughly reduced by 68.78% in the deep sleep mode,because only the always-on domains is powered up in this condition;the Sleep mode is reduced by22.08%;the Sleep1 mode is reduced by 11.91%;and the Active mode is reduced by10.16%.While implementing the Power Shut Off technology to reduce the static power consumption,the comparison between the power-up analysis results completed by the power consumption simulation software and the simulation results of the power switch calculation model proves the correctness and practicability of this calculation model.In summary,the implementation of Power Shut Off technology can significantly reduce the static power,and selecting the appropriate types of Power Switch in the daisy chain model is beneficial to the control of the rush current.