A Radiation Hardened SRAM Design

With the development of integrated circuits, memories are occupying an increasingly important position. Among them, because of its high speed and low power consumption, static random access memory(SRAM) has been widely used in various high-speed memory. At the same time, SRAM has also been applied in all kinds of space devices in circuit system. In the radiation environment of outer space, SRAM will be subjected to single event upset effects, single event latch effects, effects of total dose effect. Therefore, the SRAM used in the outer space is not only to ensure its own characteristics, but also should have better anti radiation performance.This subject stems from one outer space project, which needs SRAM, was carried out with the design of reinforcing radiation resistance. The most important part of the SRAM is a memory cell. First, analyzing the performance of the standard of 6transistors SRAM memory cell, and the memory cell circuit with a variety of reinforcing radiation resistance. The design of SRAM memory cells has reinforcing radiation resistance, and meets the requirements of the project target. With the memory cell as the core, peripheral circuit design has reinforcing radiation resistance, and it constitutes a complete SRAM design. Based on the circuit design, I achieved the physical layout. Focusing on there inforcing radiation resistance layout to improve the anti single particle properties. Finally through simulating the layout netlist with parasitic parameters, I check the function and performance of SRAM, to satisfy the design index.This paper focuses on two aspects. One is focusing on the design of radiation resistance to SRAM on the layout. In layout(1),through the protection ring or protection zone, increasing trap or substrate contact protection zone by trapping or putting a substrate contact.(2)Increasing the number of the contact(CT)which in trap or substation,(3)Pulling N type metal oxide semiconductor(NMOS) and P type metal oxide semiconductor(PMOS) distance, and other many kinds of reinforcing radiation resistance measures, making an SRAM, which has a good ability to resist single particle effects(SEE).The other is designing code for both error detection and correction (EDAC) circuit, using the Hamming coding style, with correcting an error, checking the two wrong ways of working, to have a better anti single event upset(SEU) effect ability. And the basic logic unit that is in a radiation-hardened library constitutes EDAC layout.This project is in core Semiconductor Manufacturing International Corporation(SMIC) based on 130μm technology, using Candace tools for the design of this project. eventually completed the circuit design and layout of SRAM implementation. Simulation based on tropical parasitic parameters of the net list, and then compared with a commercial SRAM with the same structure, than the commercial reading and writing in the slowest time of 2 seconds. Finally, the simulation of gold(Au) particles incidents memory cell and through the single particle simulation software, the simulation results find no occurrence of latch up effects. It has the capability of anti single particle effect good.