Design Of Fourth Order Feedforward Low Power Sigma-Delta Modulator

Analog to digital converters(ADC) are classified into Nyquist ADC and Sigma-Delta ADC in accordance with different sampling frequencies. A Sigma-Delta ADC is comprised of a modulator and a digital filter. Making use of oversampling and noise shaping, modulators attenuate quantization noise in the signal bandwidth. The high speed and low-precision output of modulators is converted into Nyquist speed and high-precision digital signal under the filtering and down-sampling of digital filters.Compared with Nyquist ADC, Sigma-Delta ADC has the advantages of better meeting low speed and high-precision applications and stronger robustness to process variations.In the interface circuits of MEMS inertial sensors, the ADC mainly uses Sigma-Delta converter. The decrease of the power of Sigma-Delta modulators is beneficial for controlling the working temperature and enhancing the stability of MEMS inertial sensors. With the development of mobile electronic devices, longer battery life is more important. Decrease of the power of Sigma-Delta modulator helps to prolong battery life. In the applications of advanced fields such as biomedicine,micromation of devices puts forward higher demand on power. So design of Sigma-Delta modulator with low power dissipation emphasis has important practical significance.The basic theory of Sigma-Delta modulator and impacts of nonidealities in circuits on performance of modulator are analysed in this paper. System level design and simulation of a fourth order feedforward Sigma-Delta modulator are accomplished.The low power design of modulator is also studied here. The power can be optimized in two ways, system structure and circuit structure. The low power techniques such as dynamic biasing, switched op and double sampling are analysed and compared. The scheme of double sampling modulator is determined. Based on CSMC 0.5μm process,the schematic, layout and simulation of the Sigma-Delta modulator are finished.The designed Sigma-Delta modulator meets 100 k Hz signal bandwidth. And the sampling frequency is set as 20 MHz. As a result of double sampling, the clockfrequency is half of the sampling frequency, 10 MHz. The simulation results reveal that the low power modulator achieves 99.6d B SNR,-110.1d B HD3 with a power consumption less than 8.1m W. The FOM reaches 170.5d B.