Research And Design Of Memory Controller Oriented To Streaming Media Application

In recent years,with the advancement of technology, the processor performance increases rapidly, but, the performance of memory is far behind in the processor’s. The memory system becomes a performance bottleneck of high-performance processor design. The importance of memory system in high-performance processor is becoming larger, so adapting appropriate storage scheduling algorithm is a significant means to improve memory access performance. Currently, streaming media applications has become the processor’s main load. The data recordings of streaming media applications,which is different from traditional application,load “stream” data processing forms while accelerating parallelize processing procedures. It’s depended on the requirement of memory system. Therefore, this paper is for streaming media applications in processor memory system to study.The main work of this paper include:(1) Research JEDEC standard protocol specification. Understand DDR SDRAM’s working mechanism and key technologies, and provide a theoretical basis for the overall design of the memory controller.(2)Analyse the memory access characteristics of streaming media applications. Analyzed by static and dynamic streaming media compression standard memory access behavior, its data memory access is different from traditional memory access.According to the access data mapping in the memory, we can understand the characteristics of memory access better.(3) According to JEDEC standard protocol specification, design the overall architecture of DDR memory controller. And based on memory access characteristics of streaming media applications, optimize the control module of memory controller. Referenced DDR3 memory controller PHY layer provided by Xilinx, implement DDR memory controller’s RTL-level design.(4) Do software simulation and hardware verification of the memory controller, and gives results of the analysis. Based on Xilinx board, the system frequency is 125 MHz, measured by the optimized DDR3 design of the maximum path delay is 6.649 ns, the minimum period is 9.143 ns, the total power consumption of the resources is 5.542 W, leakage power is nearly 50% of the total power consumption power.