Research Of Fault Injection Technology Based On FPGA

In recent years, the FPGA technology has been rapidly developed and used in such areas as aerospace, finance, national defense and people’s livelihood. However, the disadvantages of FPGA components could easily lead to breakdowns when the system runs in varieties of complicated environments. The normal solution is to equip Fault Tolerant Systems(FTS) in the computers. To exam the reliability and the fault-tolerant ability of the system, Fault Injection Tools(FITs) are needed to make online injections accurately in real time, which is the focus of this paper.In the paper, I gave a simple analysis of the current mainstream SRAM-type FPGA and pointed out its Single Event Upset(SEU) soft error and Single Event Latch-up(SEL) hard error which could easily happen. Then I divided the FPGA system into a source-code(SC) known white-box target system and a SC unknown black-box target system. To the former, by analyzing the mainstream SC modification technology, I decided to combine the branch-statement modifying strategy which supports mutation technique with the Hardware Description Language(HDL) in order to pass the bugs from the gate level to the I/O pins. To the latter, firstly I gave a comparison about the pros and cons of some FITs based on traditional hardware or bus; then I introduced the features of Bus 1553 B, proposed a fault injection scheme based on interface simulation technique which includes hardware interface and protocol interface. On the basis of these two techniques, I developed two sets of FITs which could inject faults such as fixed 0, fixed 1 and turn in the bus communication process, using FPGA. Within the FPGA, the tools support fault-superimposing and triggering of up to 16 signals. In the 1553 B bus communication process, the tools support the fault injection of the synchronization head, parity check bit, data bit, data word(DW), command word(CW) and status word(SW) simultaneously.In the last part of this paper, I described the usage of the tools I designed and the success of injecting faults. I verified the control system and the fault-tolerant ability of the bus then summarized the result: for any different FPGA system, the fault injection could be realized, no matter we add injection units inside the system or modify signals at the simulated interfaces.