Sensitivity Analysis For Processor Based On VHDL Fault Injection

With the development of integrated circuit technology, the processor isbecoming more and more sensitive to the power line disturbance, temperaturevariations, radiation and electromagnetic interference. At the same time, theprocessor in the field of aerospace applications puts forward higher requirements forreliability. Therefore, reliability is becoming an important issue that is equal toperformance when design the processor. In particular, the processor is veryvulnerable to the impact of single event upset in the space environment, so that thecontents of the processor logic unit rollover occurs, resulting in processor failure.Before the design of a fault-tolerant processor, we need to analyse the depth of thesoft error sensitivity, especially the behavior of processors in the SEU effects. Faultinjection is an important technology for the reliability assessment of processor, so itis of great significance to research and design of the fault injection tool.Through analysis and comparison with the current mainstream methods andprinciples of processor reliability assessment, this paper select the simulated faultinjection technology for the processor sensitivity analysis. On this basis, a faultinjection tool used for VHDL processor model is proposed. The tool is based on thetransient bit flip fault model; simulator command technique is employed; ModelSimis used as the simulator. In order to achieve the automation of fault injection, perl isused to realize the core algorithm of fault injection, such as calling the fault modelsand simulator. The simulator command interface uses Tcl to achieve the interactionof fault injection tool and simulator. At the same time, an optimized accelerationstrategy based on the observation point is proposed to overcome the shortcoming oflong simulation time, which can reduce the fault injection experiment time.Finally, fault injection experiments carried out on LEON3processor, and thispaper gives the sensitivity analys is result for the Integer Pipeline (IU), instructionCache and Data Cache in different benchmark. Moreover, the most sensitiveregisters are hardened by triple modular redundancy technique, and fault injectionexperiments are applied again, which verify the validity of the fault injection tool.The fault injection tool presented in this paper is used for RTL-level soft errorsensitivity analys is of VHDL-based processor, with the advantages of simpleoperation, low cost, good controllability and observability.