Research Of Transaction Level Modeling With SystemC

With the complexity of the integrated circuit increasing according to the Moore's law. the IC industry step into the SoC era. An entire heterogeneous system including software and hardware can be integrated onto one single chip, which consist of millions of transistors. However , the design ability lags behind the productivity. There is a huge design productivity gap between them. On the other hand, a large proportion of SoCs are customer products such as portable communication devices, audio or video players, which need very short time-to-market. Hence, more effective design methods are required.IP reuse is the key to successful SoC product development. IP needs proper description for users' selection and performance evaluation at system level.Platform-based design is considered as an effective method which can reduce risk and time-to-market. By reusing a particular platform, user can develop a family of products quickly.Multiple design languages are used in traditional design flows, there are communication gap between different teams. Traditional RTL design is not able to handle the complex SoC because of slow simulation speed. As SoC is a hardware and software heterogeneous system, hardware/software co-verification and co-simulation is required. Current hardware/software co-verification begins too late in traditional design flow.SystemC is a uniform hardware/software modeling language, which spans from concept to implementation. Using it can produce a executable specification. SystemC enable earlier hardware/software co-verification and faster simulation performance.System level modeling greatly reduces the complexity by raising the abstraction level. Transaction level modeling hides unnecessary details. The communication at transaction level is method calls in comparison with signals and pins at RTL. Transaction level models are used to evaluate the system architecture. SoC software engineers use transaction level models as a fast prototype to verify software early in design flow. SoC hardware engineers also employ transaction level models to build fast simulation environment.This thesis dwells on the design and implementation of AMBA on-chip bus transaction level models and the construction of the transaction level design platform. The platform consists of AMBA on-chip bus models, RISC CPU model and memory module. The platform is easy to extend and have a good simulation performance.The experiments reveal that the AMBA bus models are cycle-accurate internally and compliant to AMBA specifications. The performance is close to the commercial tools. The platform is proved to be extendible by integrating a MP3 decoder module into it. The experiments also reveal that system architecture evaluation and hardware/software co-verification can be performed on the platform.