The System Level Application Design And Verification Of Turbo Codec Using The Systemc Platform

The thesis presents methods and flows of Turbo Codec IC design with System-C Platform. And then researches the algorithms of Turbo codec to give them a chief simplification of implementation to optimize the memory and speed of system. After that, then implements the Turbo codec with System/RTL design using SystemC according its functionality of SLD and RTL capability. To prove the System/RTL capability of SystemC especially, this thesis analyzes the structure and signal flows of Turbo codec, do simulations of the Turbo modeling until finally completes the hardware design and implements the core algorithms on a FPGA platform using same simulation testbenchs for verification. It is an innovation direction to both application of Turbo codec and IC design flow of core algorithms using SystemC. The most important thing is that this design method can save more design times for its merging the SLD and RTL design and verification into one step. It also can provide a wider space for developing IC design methods in the future.