Research On Modeling And Management Technology Of SoC Transaction Level IP Core

SoC integrates the functions of a digital system, including signal collection, conversion, storage, processing and input/output, into a single silicon chip. So SoC has many advantages, such as fast, high integration and low power. In fact, SoC has become an important research area in microelectronics technology. Nowadays the integration of SoC increases rapidly, and its design complexity gets larger. To solve these problems, we need to adopt hardware/software co-design to do system level SoC design. There have two primary methods, Block-Based Design and Platform-Based Design.BBD method emphasizes IP reuse, it constructs SoC system through IP cores integration technology. PBD is BBD's matureness and extendability, it extends design reuse idea and emphasizes system reuse. But it is very difficult to synthetize directly form system model to SoC system software aim code and synthetical RTL system structure. To slove this problem, we put forward Hiberarchy Platform Based Design(Hi-PBD), intsert transaction level between system level and object level to reduce the difficultys, advance SoC system synthesize realizablty.This paper faces Hi-PBD SoC system design method, construct SoC High level hardware/software co-design platform's application requirements. There is the main work and achievements as follows:Based the study of old RTL level IP core's modeling methods, we study deeply transaction level IP core's modeling methods, put forward transaction level IP core modeling method faced SoC. Design and implement transaction level IP core modeling tool. The modeling tool includes transaction level IP core's visual design, transaction level IP core's assemblage, bring transaction level IP core hardware describe code automly(use SystemC language) and other functions. We take example for Jpeg encoding IP core, validate the tool's correctness, and optimize and consummate its functions.Design and implement transaction level character describer and transaction level IP core's data management, transaction level IP core makes up of IP Description Cell, IP Description Schema and IP Description Schema Aggregation, IP Description Cell is the smallest unit composing IP data-base, IP Description Schema makes up of many IP Description Cells, IP Description Schema Aggregation makes up of many IP Description Schemas. IP Description Schema Aggregation integrallty defines IP core's data structure in the IP data-base. In the IP core's data management, we construct IP data-base tree structure, take the IP function as main search factor, warpping the IP cores having same function in the same XML file, and set up the accessing popedom, avoid the redundancy information, advance the search...