MOSFET current source gate drivers and topologies for high efficiency and high frequency voltage regulator modules

With fast development of semiconductor industry, the transistors in microprocessors increase dramatically, which follows the Moore's law. As a result, the operating voltages of the future microprocessors follow the trend of decreasing (sub 1V) while the demanding currents increase (higher than 100A). Furthermore, the high slew rates during the transient will reach 1200 A/us. All these impose a serious challenge on a Voltage Regulator (VR) or Voltage Regulator Module (VRM). In order to meet requirements of the next generation microprocessors, four new ideas are proposed in this thesis.;The second contribution is a new continuous CSD for a synchronous buck converter. The proposed CSD is able to drive the control and Synchronous Rectifier (SR) MOSFETs independently with different drive currents enabling optimal design. At 12V input, 1.5 V/30A output and 1MHz, the proposed CSD improves the efficiency from 79.4% using a conventional voltage source driver to 83.9%.;The third contribution is a new discontinuous CSD. The most important advantage of the new CSD is the small inductance (typically, 20nH at 1MHz switching frequency). A hybrid gate drive scheme for a synchronous buck converter is also proposed. The idea of the hybrid gate driver scheme is to use the CSD to achieve switching loss reduction for the control MOSFET, while use the conventional voltage source driver for the SR. At 12V input, 1.3V/25A output and 1MHz, the proposed CSD improves the efficiency from 80.7% using the voltage source driver to 85.4%.;The final contribution is new self-driven zero-voltage-switching (ZVS) non-isolated full-bridge converters for 12V input VRM applications. The proposed converter achieves the duty cycle extension, ZVS operation and SRs gate energy recovery. At 12V input, 1.3V output and 1MHz, the proposed converter improves the efficiency from 80.7% using the buck converter to 83.6% at 50A.;The first contribution is an accurate analytical loss model of a power MOSFET with a Current-Source Driver (CSD). The impact of the parasitic components is investigated. Based on the proposed loss model, a general method to optimize the CSD is presented. With the proposed optimization method, the CSD improves the efficiency from 79.4% using the conventional voltage source driver to 83.6% at 12V input, 1.5V/30A output and 1MHz.