Design And Realization Of Multi-channel Broadband Signals Generator

Currently, high-performance broadband signal source has become a key role in the radar system. This dissertation introduce the method of the digital IF(intermediate frequence) signal generation technology and deeply investigate the method about multi-channel DDS synchronization and multi-target echo generation with a single DDS chip. The background is the design of a multi-channel synchronization broadband signal source system.This dissertation introduces wideband IF signal generation technology- Direct Digital Waveform Synthesis Technology(DDWS) and Direct Digital Frequency Synthesis(DDS), and contrasts the output signal characteristics of the DDS and DDWS. And, this arcticle introduce the excellent DDS chip- AD9910’s structure and function. Furthermore, a meathod to simulate the linear frequency modulation(LFM) multi-point target echo based on a DDS chip is introduced. The multi-target echo form of LFM is analyzed. The simulated echo is obtained from generating the LFM part with AD9910 in the digital ramp modulation mode and superimposing multi-target information through phase modulationIn order to obtain multi-channel synchronous broadband signals, the dissertation focuses on the method about synchronization of the DDS’s output signals. DDS has an internal multi-chip synchronization module what can regulate the internal system work status with synchronization reference signal – SYNC_IN from peripheral circuits. If SYNC_IN signals are synchronized, then the operating state of the DDS is synchronized. If the external circuit provides reference clock signals, SYNC_IN signals and trigger signals synchronized and the multi-chip synchronization module is configured correctly, the output signal of DDS will be synchronized.This dissertation introduces the design of multi-channel synchronization wideband signal source system from the structure of the system, the main chip selection and the design of key circuit module. The article describes the design details of some circuit, such as the DDS synchronization module, FPGA configuration module, DDS control module and clock management module. The USB interface chip and FPGA is the control core of the system. The clock management chip in the control of USB interface chip output clock signals required. Then, USB interface chip becomes the data transmission channel between the host computer and the FPGA. Except the communication with the host computer, FPGA also achieves other logic functions such as the control of DDS and DDR3.