| Synthetic Aperture Radar (SAR) imaging technology has evolved to satisfy a variety of application for both civilian and military users. The echo signal simulation is very important to the study of the SAR system and the imaging methods ,is the foundation of the technology of SAR simulation. SAR echo simulator can support SAR system design with database, is the necessary instrument for the design, research and test of SAR system.In this dissertation, we study hardware implementation of target signal generator for SAR echo simulation. The main content is as following:1.According to algorithm for SAR echo simulation and the requirement of our project, after estimating system requirement for computation and memory, we establish system framwork. The tagert signal is generated by DSPs Parallel Processing Board, convoluted with LFM signal in FPGA Board, and converted to echo signal by DAC.2.Design DSPs Parallel Processing Board, including: Clock, SDRAM, DSPs loader, Power, JTAG, Reset, FLAG and PCI.3.PCB design and syterm debug. We optimize tradeoffs in cost, DFM (Design for Fabrication), and performace. A daisy chain topology and 14 layer stack-up is used for PCB. Signal Intergrity is performed in HyperLynx. System is debuged by modules, and the performance of the Parrallel Processing Board is verifyed by point echo simulation. The result illustrates that the Board can meet the project requirement.Implementation for the target signal generator board for SAR echo simulator gives a foundation for airbone SAR echo simulation system, and can be applied to related fields such as real-time processing and high-speed signal processing. |