The Design And Verification Of Multiplier Unit Based-on X-DSP

X-DSP is a high performance multi-core digital signal processor, which supports fixed-point and floating-point operations. The Multiplier Unit is an important part of the DSP. To meet the X-DSP requirements on the parallelism, real-time, efficiency and stability, a high-performance SIMD multiplier is designed and completed in this paper. The main contents are as follows:1. The design of multiplier includes three arithmetic parts: the Multiplication operation, the Galois Field operation and the Logic operation, as well as exception-handling mechanism. The Multiplication part has designed a high performance SIMD multiplier architecture. The multiplier is composed of sixteen 16-bit multiplication arrays, and it can complete multiplication of different bits and multiply-accumulate operation. In addition, to improve the operation speed of 16-bit multiplication unit, a three level compression array is devised. As a result, compared with traditional structure, the delay reduces 12%. The Galois Field part realizes the finit-field operation based on the optimized algorithm of Galois polynomial multiplication. The Logic part mainly implements bit-field and average operations, and is divided into five modules: bit extensive, bit operation, bit interactive, bit-shift and averaging. The exception handing part can detect the opcode exception and resource conflict exception, and gives the corresponding processing at the same time.2. According to the characteristics of multiplier operation, we produce corresponding directional test vectors, used as “seeds” for pseudo-random test. Then, the design unit is verified with the gold model using Assertion Verification undering the tool for equivalence checking(ATEC), to ensure that their function are fully equivalent and the design unit is correct. Finally, a FPGA Verification Platform is built for core simulation, running graphics codec, liner program, other large library program to guarantee the correctness of the design.3. The timing on critical path of the multiplication, as well as the area on non-critical path, are optimized. After a series of optimization, such as structural adjustment, balancing pipeline, and other methods, the timing is reduced by 8.3% and the logic series decrease by 46.5%, and the unit meets the design requirements.In the 40 nm CMOS process, depending on the Design Complier Topographical of Synopsys, under the Worst Case, the multiplication unit area and power have met the design requirements: the frequency is up to 1GHz, and the area is 150941.5μm2; in addition, the leakage power and the dynamic power is 4.9877 mW and 13.1461 mW respectively.