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The Design And Implementation Of SIMD Floating-point Arithmetic Logic Unit For X-DSP

Posted on:2014-01-15Degree:MasterType:Thesis
Country:ChinaCandidate:B R SongFull Text:PDF
GTID:2298330422474003Subject:Software engineering
Abstract/Summary:PDF Full Text Request
X-DSP, independently developed by NUDT, is a new high-performance universal64-bit SIMD DSP, it employs VLIW technology and can be applied in a variety offelids including high-performance computing, military industry, and video and imageprocessing. This thesis designed and implemented DSP-oriented high-performanceFloating-point Arithmetic Logic Unit (FALU) in order to meet the demands forcomputing with floating point arithmetic logics, based on research and development ofX-DSP. The main contribution of the thesis is as following.1. Based on the requirements of X-DSP, we classified the function of FALU intofour categories, including comparison operation, addition and subtraction operation,conversion operation and special operations. For each of these four categories, relatedinstruction sets were carefully designed. Then, we studied and designed the overallstructure of64-bit high-speed FALU, which can support single-precision SIMDoperations.2. We illustrated in detail on how to implement the structures of each sub-module.For each sub-module, we developed optimization methods based on their particularfeatures. Then, we demonstrated designs of core components such as adder, shifter andLeading Zero Prediction.3. We finished function verification and random number verification for allsub-modules of FALU as well as verifications for top-level module. In the process ofverification, we developed a new module level instruction simulator with GUI, whichcan significantly simplify the tedious repetition work that is necessary without thistechnique, thus improved accuracy and efficiency substantially. After iterativecorrections according to feedbacks from verification results, we achievedwell-functioning of all the components.4.We synthesized FALU and its all sub-modules by Cadence’s RTL Compiler.Under TSMC’s45nm technology, we studied strategies needed for our synthesis. Theresults indicated that the delay of the key path is450ps, cell area is47690μm2, total areais130350μm2, and total power consumption is4.34mW. This result showed that ourdesign can meet all technical requirements of FALU in X-DSP...
Keywords/Search Tags:SIMD, FALU, Verification, Synthesis
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