The Design And Implementation Of High-performance64Bit Fixed-point SIMD Multiply Accumulate For FT-XDSP

FT-XDSP is a64-bit high performance general DSP with very long instruction word (VLIW) architecture, and its frequency is1.5GHz. It will be used in high performance computing, wireless communication, video, and image processing. This thesis implements a64-bit high-performance Single Instruction Multiple Data (SIMD) fixed-point Multiply ACcumulation (MAC) unit in order to improve the performance of fixed-point multiplication and parallel computation for FT-XDSP. The main work and contribution are as follows:1. The64-bit SIMD fixed-point multiplication algorithm and architecture were proposed. The multiplier can perform either one signed/unsigned64-bit fixed-point multiplication or two parallel32-bit SIMD signed/unsigned fixed-point multiplications. The improved multiplier’s architecture used an idea of prediction and implemented SIMD multiplication with the method of sign-bit preprocessing. We also applied this64-bit multiplier to perform the53-bit mantissa multiplication of IEEE-754double-precision floating-point multiplication. The maximum delay of the improved multiplier is724ns with45nm CMOS standard cell library.2. A64-bit fixed-point MAC unit was implemented with four pipeline stages. This unit can perform many kinds of64-bit fixed-point operations and32-bit SIMD fixed-point operations, such as addition, subtraction, multiplication, multiply-add, multiply-sub, dot product and complex operations. Architecture of fixed-point MAC and pipeline were designed in the thesis. The key modules, such as design of pipeline stage and the reuse of multiplier for fixed-point operations and floating-point operations, were implemented with Verilog HDL. The single cycle module of fixed-point MAC was designed by Prefix adder.3. Optimization, verification and synthesis of64-bit fixed-point MAC unit were done with NC and RC. The key path of fixed-point MAC was optimized to satisfy the cycle restriction of FT-XDSP, We synthesized the64-bit fixed-point MAC unit using RC with45nm CMOS standard cell library at the condition of Typical. The synthese result shows that its frequency can reach1.5GHz, the delay of key path is450ps, the power is17.1mW, and the cell area is89727um2.. Detailed module verification and systemic verification under the simulation environment for DSP core had been made. The experimental results show that the functions of this fixed-point MAC are right. As a result, the proposed fixed-point MAC unit satisfies the latency, area and power requirements for FT-XDSP.