A Design Of YHFT's Multiplier Unit And ALU

YHFT-DSP is a 32-bit fixing-point high performance DSP. Its architecture is VLIW and it can issue 8 instructions in a cycle. In this paper we raised a new thought about CPU design and at the same time, we did a good research in design, verification and systhesis about the multiplier and ALU of YHFT-DSP.The multiplier unit is the most important part in CPU. Multiplication is an important criterion for evaluating DSP's performance. In the design of multiplier, many advanced techniques are researched and used with design's character.They are all the good feature which including research about partial product's production and compression, simd multiplier and 16×32 bits integer multiplication's realization, multi-instruction single-circuit,pipeline's design.The ALU is the important part in CPU either which mainly finished the arithmetic operations and some logic operations. In this design, we discuss the way of SIMD arithmetic operation's realization, modules'partition and the entire structures are very pivotal.Based on the simulations from both module level and fullchip level, the paper discussed the verification of these two units, raised the test way, developped the efficient, self-contained testbench, constructed the verification model which are all show the design is correct.At the end of this paper, we discussed the synthesis of the multiplier unit and the ALU, first of all, we concluded the optimization parts of the design, then do a synthesis to them, the results show that the two units'frequency are 303.03MHz and 384.62MHz which are all reach the goal.