The Design,Verification And Optimization Of Multiplier Unit Based-on X-DSP

Being independed positive designed, X-DSP is a32-bit high performance DSP andsurports fixed-point and floating-point operations. Its architecture is VLIW and it adoptsSIMD technology.The Multiply Unit is one of four functional arithmetic unit of CPUcore. According to design criterion in X-DSP, this thesis has designed an highperformance SIMD Multiply Unit which supports fixed-point and floating-pointmultiply operations and meets the DSP requirements of high parallelism, high precisionand real-time.The main works and contributions are as follows:1.The design of Multiply Unit. First, the thesis analyzes and reaserchs theMultiplication instruction of the Multiply Unit in X-DSP. Second, according to theanalysis result, the thesis designs the structure of fixed-point and floating-pointmultiply. Then, this thesis implements logical design of the SIMD Multiply Unit,adopting the Multi-data Multiplication arithmetic, Wallace tree and Carry Look Aheadadder.2.The timing optimization of Multiply Unit. To begin with, this thesis gains thecritical path of Multiply Unit by using the Design Compiler of Synopsys. Then, thethesis optimization design the module in the critical path. Last, this thesis optimizes thewhole Multiply Unit at arithmetic structure level and RTL code level. under theconditions that adopting45nm CMOS process and the preconditions of area and powerperformance having been satisfied, time of the critical path reduces190ps, timingperformance increases22.4%, and the number of register reduce18.3%.3.The functional verification of Multiply Unit. Two methods, simulation basedverification and FPGA emulation, can be used for functional verification of MultiplyUnit. Good test case is key to simulation, and is developed by using functional coveragemethod at module level and system level. Module level develops test bench according tothe functional characteristics of module. System level mainly verifies pipline andoperation function. Finally, a solution of FPGA emulation for X-DSP’s CPU core isgiven.In the45nm CMOS process，the result of Place and Route indicates that under theworst conditions the performance of Multiply Unit absolutely satisfy the goal of X-DSP,and parameters are as follows: The frequency is up to1GHz, dynamic/static power is12.6686/4.5032mW, and area is202718.88um2.