Structure Design And Simulation Of A 64-Bit RISC Microprocessor

Due to requirements for high speed information processing and complex intelligent control, the circuits with microprocessor as core are used wider and wider. Research and design in microprocessor architecture can promote the development of our national IC industry and satisfy market demand.The work in this thesis is part of a National 863' project which undertakes by Arkmicro Company. There are five parts in VEGA microprocessor, which hires five-stage pipeline: Integer Execution Unit (IEU), Memory Subsystem Unit (MSU), Registers, Pipeline Control Unit (PCU) and Bus Interface Unit (BIU). This paper studies PCU's design and implementation, VEGA simulation and FPGA verification. Finally, VEGA passes the test of WinCE3.0 and Linux operation system.The research work of this thesis mainly includes:1. Design a 64-bit RISC processor. Divide pipeline control unit into different modules, which includes Forwarding, HDU, Exception and so on. Exception subsystem is the most important of all.2. Exception operation in CPO. In thesis, we mainly discuss such operations as save location, switch mode, load software when pipeline exception occurs.3. Simulation of exception subsystem.4. Simulation and FPGA validation of VEGA.VEGA is a complex microprocessor system. This thesis has contributed a lot to the designing of embedded microprocessor with full copyrights. The design of VEGA system provides an optional method for urgent needed microprocessor in aviation projects.