Study Of Charge Sharing Effect Based On 3D Device Model Simulation Of TCAD

With the rapid development of integrated circuit manufacturing technology,devices feature size continues to decrease,as well as the devices spacing. When the high-energy particles in radiation environment bombar the devices’ sensitive region, the sensitive nodes will collect charges, and then case single event upset effect or single event transient effect. Because of the shrinking distances between devices, when the semiconductor technology enters nanometer scale, charge sharing effect will become one of the most important problems in the field of reliability. Charge sharing can not only lead to multi-bit upset in a storage unit, but will enable to generate multi-single event transient in a combinational logic circuit, so that soft error rate of the system will increase, thus increase the difficulty of design of anti radiation. At present domestic research to the charge sharing effect mainly focuses on a single device, and considers the process above 90 nm. It is difficult to get the influence of charge sharing effect in a smaller size process and in a storage unit. Therefore, it is necessary to carry out a specific study on charge sharing effect from these aspects, so that we can reinforce the charge sharing effect targeted.In this paper, the three-dimensional device simulation based on TCAD model is used to search the charge sharing effect deeply in 40 nm CMOS process. The 3D device model and SPICE model are both based on IBM 40 nm CMOS process. The main work of this thesis is as follows.The 3D devices models are built. Through reference to relevant information, 3D transistor device models which are calibrated with the SPICE model of IBM 40 nm CMOS technology are be established.Research on the influensce of different factors on the charge sharing effect. Studied the influence of the STI, incident angle and deep N-well concentration on charge sharing effect. Found the effective STI depth to inhibit charge sharing is 500 nm between NMOS devices, while the charge sharing between PMOS changes linearly with the depth of STI. In addition,the introduction of incident angle and N type deep well in 3-well process can increase the charge sharing between NMOS devices seriously.Research on the influence of charge sharing effect on the pulse width of the SET and recovery of the SEU in a 6T SRAM unit. The study has found that charge sharing will inhibit the with of SET, and when the charge sharing collection is serious in a SRAM unit no matter in triple well process or angle incident, the SEU will recovery. Also, in this paper, a new layout structure is build to increase charge sharing collection to help restrain the SEU in a SRAM unit. It can decrease the inversion recovety threshold more than 20%.A new way was researched to decrease the collection of charges. The study found that “guard drain” structure which is used in 90 nm process frequently is not applicable in 40 nm process. So a new additional electrode structure is created to decrease the charge collection by single event and charge sharing effect. It has been proved that the new structure introduced in this paper can decrease the charge collection in single node over 15%, and restrain charge sharing and the MBU in SRAMs.