Research On Key Issues Of Affect On Single Event Effect Induced Charge Collection And Charge Sharing In Nanometer Scale CMOS Devices

The devices used in space borne are continually affected by radiation effect,which had become the major impaction on device operation. The single event effect mechanism of larger technology node devices had been deeply studied, and a serious of single event model, radiation hardened by design technique and soft error evaluation methods have been developed. However, as the technology continues scaling down, the density of transistor increasing, operation voltage decreasing and clock frequency accelerating make the new radiation mechanism appear. It brings significant challenge of single event effect research. The critical charge decreasing makes the single event effect more sensitive than before; multiple node charge collection and charge sharing induce multiple cell upsets occurring frequently; single event transient in combination circuit has become the major error in integrated circuits; process parameter variations significantly affect charge collection and sharing; the quantization of charge collection is more difficult because of the scaling down device and the more complex structure of device. As a whole, the issue of single event induced charge collection and charge sharing had been the hot point in nanometer device radiation effect research.Focus on the above issues, this paper will carry out the researches of SEE key issues of single event induced charge collection and charge sharing in nanometer CMOS devices, and the contents of the researches are as follows:(1) Soft error prediction is an effective means for single event effect mechanism research, the performance radiation hardening evaluation, and radiation hardened by design verification. Sensitive volume can quantify the transistor charge collection, which is the basis of soft error prediction. As the technology node continues scaling to nanometer level, the new device structure and charge collection mechanism increase the difficulty of charge collection quantification. This paper proposes an sensitive volume considering the on-transistor charge collection which can improve the accuracy of charge collection. A novel schematic is proposed to calibrate the parameters of sensitive volume, which can effectively solve the problem of single event upset recovery induced charge collection decreasing. Improve the criterion of single event upset in SRAM which consider the effect of SEU Recovery on SEU cross section. The simulation results indicate that the proposed on-transistor sensitive volume is accurate, which is meaningful for single event effect mechanism research, radiation hardened designation and engineering evaluation.(2) As the transistor feature size scaling down, transistor parameter variation is more serious than before. Parameter variations significantly affect the performance of Ics, which is an unavoidable reliable issue. The parameter variations also significantly affect the single event induced charge collection and charge sharing. In this paper, TCAD simulation combined with Monte Carlo process simulations are carried out to identify and quantify the impact of parameter on single event transient and SET Quenching, which provides references for radiation hardened design in combinational circuit. Quantification research of the impact of gate oxide thickness, threshold voltage, channel length variation and channel width variation on charge collection and charge sharing had been conducted. The impact of parameter variation on DICE failure which is caused by multiply node charge collection had been studied, and propose the DICE hardened guidance schemes. Quantification research of the impaction of parameter variation on SRAM soft error prediction, represent the impact of parameter variation on SEU cross section.(3) N+ Deep well device can be used to mitigate the substrate noise which is widely used in digital circuits and analog circuits. However, the structure of N+ Deep well will enhance the parasitic bipolar effect, which can further increase the sensitive of charge collection and charge sharing. This paper deeply study the impact of well doping on single event induce charge collection and charge sharing based on a 65 nm Deep N+ well process. Heavy ion simulations are conducted on different well doping devices by TCAD, identify and quantify analysis the impact of doping density on single event transient, multiple single event transient, SET Quenching and SEU Recovery, which support the theory support on mechanism research and radiation hardened design. The parameters of N+ deep well device can be obtained by TCAD simulations, and the soft error prediction is conducted based on the sensitive volume. The results indicated that SEU crosssection increases along with the doping density increases.(4) As the technology scale down, the ratio of SET in combination circuit to the total SEE should attach great important. In nanometer CMOS systems, SET pulse width approach to signal cycle which may consider the correct signal, so that the development of SET radiation hardened technology in combination circuit is extremely urgent. This paper proposes an enhanced dummy transistor layout radiation hardened technology. Adding a reverse biased junction based on dummy transistor, the junction can collect the carriers induced by ion striking. So that it can mitigate SET. TCAD simulations indicate that compare to other layouts, the enhanced dummy transistor has the least SET pulse width. The SET even can be eliminated for the special striking angular. The proposed layout can be extended to multiple combination logics.This paper focus on the key issues on single event effect induces charge collection and charge sharing in nanometer CMOS devices. An on-transistor SV is proposed, which reveals the impact of on-transistor charge collection on single event effect. The impact of N+ Deep well device doping density on charge collection is deeply studied. identification and quantification analysis are carried out to show the impact of parameter variation on single event effect.A novel enhance dummy transistor radiation hardened by design technique is proposed, which can improve the radiation hardened ability of combinational circuits. The main content include charge collection and charge sharing, radiation hardened designation, parameter variation and soft error prediction. The area of researches in this paper is from nanometer CMOS device physical mechanism to SEE prediction, which is not only the development direction of integrated circuit radiation effect field, but also the demands of space application in our country. So that, the researches in this paper not only have theoretical study of forward-looking, but also have better practical merits.