SRAM BIST Circuit Design Based On The March C-Algorithm

With the development of integrated circuit design techniques and process technology, semiconductor memories represent a significant part of typical SoCs, any improvement in the design and manufacturing processes of memory devices has a straightforward and significant impact on numerous features such as cost, yield, performance, and reliability of the whole SoC. For this reason, memories have been designed with the most up-to-data technology so as to achieve the highest storage density and access speed. The main consequence is that memory devices are statistically more likely to be affected by manufacturing defects and process variations, which becomes the main problem of the overall SoC field.Nowadays, Static Random Access Memories (SRAMs) testing has become an important subject. Among the current testing technologies, Built-In Self-Test (BIST) is a both time-saving and cost-saving means. By taking into account the embedded SRAM fault model, the March C-algorithm is chosen to diagnose the embedded SRAM in this thesis, and the March C-algorithm is extended to word-oriented algorithm. It has a higher coverage for common faults of SRAM and moderate difficulty in hardware implementation. This paper focuses on the overall design of an SRAM BIST circuit based on Finite State Machine (FSM). The SRAM BIST circuit is built using Verilog HDL language and simulated by ModelSim software. FPGA platform is made use of for BIST timing analysis and functions verification. Finally, through synthesis with Design-Compiler, netlist extraction, static timing analysis, automatic placing and routing are conducted to achieve a layout of the BIST system.There is in this paper the evidence that the MBIST circuit design on the basis of the March C-algorithm is practicable. It covers the most of the common SRAM fault. It is advantageous in testing time and chip area.