Reduce Technology Of Leakage Power Dissipations In CMOS Ics

The pace of MOSFET technology scaling and new product development has accelerated in recent years and shows no sign of slowing down. As a result, successively higher levels of integration have been driving up the power consumption of chips. Power is rapidly become a design constraint not only in the domain of mobile devices but also in high performance processors. Large dynamic power is caused by switching activity in CMOS circuits. It is the major source of total power dissipationin today's process generation. However static power, which is due to leakage current in the quiescent state of circuits, is gaining more importance. We have seen earlier that the scaling of supply voltage and transistor threshold has a large impact on the leakage current.First, the rapid development of technologies such as Wireless communications and computer networks requires for the capability to deal with large information. Multimedia technology development on the demand for high-performance chips is increasing the clock frequency of the chip, which leads to larger and larger power dissipation. Therefore, the design of low power intergate circuits has become more and more important.Second, in recent years, portability has become important. Historically, porttable applications were characterized by low throughput requirements such as for a wristwatch. This is no longer true. Among the new portable applications are hand-held multimedia terminals with video display and capture, audio reproduction and capture, voice recongnition, and handwrting recognition capabilities. These capabilities call for a tremendous amount of the computational capacity. This computational capacity has to be realized with very low power requirements in order for the battery to have a satisfactory life span. With technology scaling, the leakage current becomes more and more large contributor to the power dissipation of CMOS circuits. Thence the standy power of portability has started to attract the attentions of designers of low power ICs and consumers.The Last, high leakage current in deep sub-micron regimes is a significant contributor to the power dissipation of CMOS circuits as the CMOS techniques scales down. Consequently, the identification and modeling of different leakage components are very important for estimation and reduction of leakage power, especially for low power applications. Related studies have shown that at 90nm node, leakage power comsuner the 1/3 of the total power dissipations. At 65nm node, the gate leakage current can become the dominant part of leakage power rather than the sub-threshold leakage current.This paper explores nanometer scale CMOS circuits leakage mechanisms, device and circuit techniques to reduce leakage power consumption. Based on the previous leakage techniques, we can propose a new full adder and two new D flip-flops. Compared with the precious circuits, they has the lower leakage power. At last, we can utilize P-type CMOS techniques to reduce the leakage power of the adiabatic circuits. The main contents of this paper are shown as follows: The mechanism and sorts of the leakage current are introduced in deep-submicron process. According to the leakage mechanism, the leakage currents can be classified into eight kinds: Hot-carrier injection, Gate oxide tunneling, Narrow-width effect, Punch through, gate-induced drain leakage, drain-induced barrier-lowering effect, weak inversion and pn reverse-bias current. According to the design of circuit, it contains the gate leakage current, sub-threshold leakage current and BTBT leakage current.The previous leakage reduce techniques are presented in this paper. There are Multiple Threshold CMOS—MTCMOS, Dual Threshold CMOS—DTCMOS, Variable Threshold CMOS—VTCMOS, Stacking Transistor Techniques—STT and Input Vector Control—IVC. Apart from these, a well processor technique is also introduced simply. The applications of the leakage reduce techniques in combination circuits are shown in this paper. Since that the PMOS has the litter magnitude of the gate leakage than the NMOS, P-type CMOS techniques is adapted to the new PCPL and PDCVSL full adders in order to reduce the gate leakage power consumption.The applications of the leakage reduce techniques in sequence circuits are shown in this paper. The new dual-threshold D flip-flop and the MLRT (the multiple leakage reduce techniques) D flip-flop are proposed in order to reduce the leakage power consumption of the sequence circuits in this paper.The applications of the leakage reduce techniques in adiabatic circuits, which is in order to reduce the leakage power consumption. Referenced to the experience of the research of conventional CMOS circuits, P-type CMOS technique is adopted for the reduction of adiabatic circuit.