| The project is cooperated with an institute of scientic research of military affairs, which is applied in fire set of artillery system. It has very important value in military affairs. The difficulty of this circuit lies in the high requirements of leakage current and on resistance. For such purpose, two design schemes: single chip and double chips have been proposed. The circuit of single chip whose working voltage is 30V is made by BiCMOS technology. Combined with current technology processing condition, a special technology flow has been designed according with the demands of all the parameters, passing the examination of TSUPREM4.The design and analysis of Vertical PNP Transistor was accomplished through the relationship between carriers lifetime of epitaxy layer and current gain, rate of surface combination and leakage current, carriers lifetime of epitaxy layer and switch speed. Meanwhile, the relatioship between Al's width of emitter and collector current, which called "Extended Electrode Enhancing Current", has been presented. The simulation of circuit has been accomplished through Hspice2001.4 and Cadence. A silicon self-aligned technology was achieved by using a SMART power integrated technology to get high power of the circuit. Vertical PNP Transistor whose base is epitaxy layer was used as output. The collector of the Vertical PNP transistor was set on the back of the chip with low resistance P+ substrate as ohm contact. Finally, layout was finished through Virtuso Editor in Cadence, passing the verification of DIVA. The whole processing will be finished in the partner.It is an emphasis on lowering leakage current and how to prevent the circuit from touching off with error in this thesis. After success in processing by BiCMOS technology, the research on how to improve the circuit with SOI(Silicon On Insulator) technology will be carried out ulteriorly, making more useful widely in the construction of national defense. It has great importance in politics and military affairs. |
PDF Full Text Request