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Research And Desigh Of High Speed Spread Spectrum Clock Generator

Posted on:2016-08-05Degree:MasterType:Thesis
Country:ChinaCandidate:S YangFull Text:PDF
GTID:2308330473959707Subject:Microelectronics and Solid State Electronics
Abstract/Summary:PDF Full Text Request
As electronic devices work faster and faster, the frequency of electromagnetic interference(EMI) which is caused by them gets higher and higher. In order to eliminate EMI, people adopted many methods, such as low voltage differential clock, staggered high frequency output, special technology for layout design and the spread spectrum clock. Among these ways, spread spectral clock can eliminate higher harmonic energy, thereby weakens EMI more effectively.This article designed a 800 MHz, 15 db EMI attenuation phase locked loop meeting the requirement of the LPDDR3 timing. I Built the PLL in matlab behavior model, achieved linear model for all the modules, and completed the function verification of the whole system. The whole phase-locked loop transfer function is derived, bandwidth, the relationship between phase margin and other key indicators and charge pump’ charge and discharge flow, oscillator gain and the parameters of the filter is definite. I optimized the pulse width of the dead zone of frequency phase detector and, from the perspective of the power restrain improved the voltage-controlled oscillator phase noise performance, and further analyzed the oscillator gain value what are the effects of the imperfect. With an intrinsic narrow bandwidth, the characteristics of normal work more time consumption to lock, self-designed improved fast locking module. I Designed high speed frequency divider, improved working speed restrictions logical node, made the frequency divider was able to work at about 1.04 GHz frequency, leaving allowance of 30%.In this paper, 90 nm high voltage process was adopted. The final design of phase-locked loop completed simulation under various environment, spectrum spread’ work status both on and off were done the simulation verification. The phase-locked loop can normal output 800 MHz clock signal, with 15 db attenuation of the EMI, spectrum spread case simulation got cycle to cycle jitter of peak to peak value of 58 ps, root mean square value of 25 ps, the paper’ goals are met.
Keywords/Search Tags:electromagnetic interference, phase locked loop, spread spectrum clock, EMI reduction, fast lock
PDF Full Text Request
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