EHCI Verification Environment Research And Development Based On UVM Architecture

With the rapid development of chip technology, the chip with more complex functions, pre-IP RTL-level functional verification plays an important role in the entire chip production process. Traditional verification has been unable to meet the needs of the market, based on the random verification method of SystemVerilog language has became a mainstream in the digital IC verification. UVM verification architecture based on SystemVerilog language which is extensible and reusable is used widely by many IC design companies.The electronic products based on USB2.0(Universal Serial Bus) transport protocol have been widely used in daily production and the life. The descriptor concept of EHCI(Enhancement Host Control Interface), enhances USB2.0 products transmission efficiency greatly. Of course, as a high-speed EHCI host controllers, need to meet the EHCI specification, USB2.0 protocol, UTMI bus interface protocol and other system bus protocols that increases the EHCI IP design complexity, so that the EHCI RTL functional verification is more challenging. Traditional EHCI host controller verification adopts direct testing which cares part function only, and then guarantees the quality by FPGA emulation. The two methods are not only low efficient, but also not cover the entire features of the EHCI host controller. The bugs in the USB product will exposure always in the application so that affects product quality and company credit. It is very necessary to verify design entirely to guarantee product more reliable and improve company credit.To solve the above problems, the subject developed EHCI RTL-level functional verification program based on UVM verification architecture, list functional test points completely, build EHCI controller verification environment, and verify the function of the EHCI host controller strictly, the final run a large number of simulations to ensure its functional coverage to 100 percent for bug free.A period of nearly ten months from the theoretical analysis to the specific practice, a half-human consumption, the subject made great achievements. EHCI controller using the UVM architecture to do a complete functional verification, in a relatively short period of time found more than one hundred EHCI controller function defects, achieve one hundred percent functional coverage, code coverage is also in line with expectations. After preliminary full functional verification, FPGA post-test goes well, and the related modules such as host driver module, device driver module, and some modules about the VIPs are reused in the OHCI controller, OTG controller function verification, thus save more manpower and time, reflects the basic idea of UVM verification methodology.