| With the significant increasing of the complexity and scale of SoC(System on-a-Chip) design, the function verification work which is themselves tedious now becomes a even greater challenge. Although the technology of traditional verification methods is keeping updating to adapt the condition, the verification work is also consuming up to even more than 70% time of the whole SoC design flow. Therefore ,to meet the requirements of ever-shortening product development time and then enhance the product competitiveness, improving the efficiency of verification and reducing verification time is the highest priority.In order to improve verification efficiency, the thesis studies efficient verification system, and gives a verification system architecture and implementation based on SystemVerilog OVM.. The system has high reusability, which includes system architecture, interface verification components and modules to integrated verification system. its good scalability can easily verify the flexibility to generate lots of different scenarios; In addition, the system can be verified with high degree of automation, such as constrained-random test and coverage-driven method.The thesis introduces concepts in traditional verification methods ,which is always in lack of reusability, scalability, and also having low degree of automation, so the work is to be large and inefficient. Thus, the thesis researches some popular technologies and OVM, then puts forwards one improved verification system with whose structure is on a high reusability and scalability, and also easy to be used to build an automated system. Then, this thesis gives the detail implement with the basic OVM class library and makes analysis of the test results of a real project. |
