The Design And Verification Of IIC Bus Based On UVM

Since the 21 st century,significant changes have taken place in the global IC industry.Various emerging technologies have promoted the development of chips in the direction of smaller size and larger scale.Verification is the key line of defense to ensure the correct implementation of chip functions.Verification also takes up a lot of time in the actual chip project cycle.Improving the verification efficiency is of great significance to reduce chip costs.UVM(Universal Verification Methodology)was born under the background of a special era,adopted a variety of advanced verification ideas and methods,stood out from many verification methodologies,and has become one of the mainstream verification methods in the current industry.In addition,in view of the simple structure of the universal serial bus IIC(Inter-Integrated Circuit)bidirectional two-wire,its unique data transmission mode and its extensive use in the system-on-chip,this paper selects IIC bus interface as the design object,and focuses on the implementation and optimization of its verification platform based on UVM methodology.In terms of design,this paper first deeply analyzes the bus structure,interface protocol and transmission format of IIC,completes the overall circuit structure design and sub-module function division,designs each module state machine and uses Verilog language to implement RTL code writing.In terms of verification,before the verification environment is set up,a verification plan is first developed according to the characteristics of the design under test,and a total of 19 verification function points are extracted.After constructing the overall architecture of the verification platform,the System Verilog language is used to model and connect all verification components hierarchically,and finally,a randomized and efficient verification platform supporting multi-master operation scenarios is built,and a series of test sequences and 9 test cases are also designed and executed.The design under test is simulated and verified in multiple scenarios and all aspects.This paper also combines with the advantages of Assertion Verification and developes a series of attribute-based assertions on the basis of the existing verification platform.Through the assertion checker,the timing-related function points and the jump of state machine in the design are supplemented and verified to ensure the completeness of verification.Some optimization strategies are proposed for the traditional register verification scheme.According to different fault types,four parts are divided into register reset value check,access check,bit-cross check and random check.The verification ideas and optimization methods of each part are analyzed,and the corresponding test sequences are designed.Finally,corresponding test cases are written for the internal registers of the design under test,and simulation verification and coverage collection are performed.All the simulations in this paper are carried out using Synopsis' s VCS tool.After the simulation,the verification results are briefly analyzed from the three dimensions of simulation report,key waveforms and coverage data.After register verification and basic test cases are passed,regression testing and adding test cases are used for uncovered points.Finally,the code coverage,function coverage and assertion coverage are all 100%.The goal of verification plan is completed,the optimization of register verification is realized,and the verification tends to converge.