The Efficient Unit Verification Platform Design Based On The Vmm

With the booming of the IC design scale, functional verification has been faced increasing challenges. Traditional verification platforms have more and more obvious disadvantages in reusability, scalability, efficiency and so on. These disadvantages have become the bottleneck of ASIC development. Aiming to bridge the gap between the design scale and verification techniques, verification engineers and some EDA companies continuously propose the advanced verification languages and verification methodology to improve the validation efficiency.SystemVerilog is adopted in this dissertation to design a hierarchical verification platform, which is based on the VMM for the PLAOM module of a chip of GPON OLT MAC. The verification platform is transaction-based, automatic and reusable. The platform can improve the verification efficacy greatly. However, traditional VMM platform only abstract the data stinulation processed by DUT into transaction,and classify internal registers configuration into the list of the BFM components. Furthermore, it has one drawback in the verification of the signals between interfaces. The main task of this dissertation is to make some improvement to the traditional VMM verification platform. The contributions are as follows:firstly, the improved VMM platform abstract the data stimulation as well as registers configuration into transaction, and design the independent sub-module of CPU_ENV, which can easily reused by other verification platform. Then, the improved platform changed the way of configuring internal registers by the new component CFG, which extends from the class vmm_data from VMM. Besides, in order to achieve the equilibrium between efficiency and quality, the platform using coverage driven verification in the registers configuration. At last, the improved platform adopts the assertion based verification between the interfaces to verify whether the signal is correct in timing.In this dissertation, some brief review is given about the simulation-based functional verification technology, the VMM verification methodology based on the SystemVerilog, GPON system and PLOAM. Detailed description of VMM verification platform for software design is followed. According to the shortage of the traditional verification model, a detailed realization of the improved verification platform is given. Meanwhile, coverage driven and assertion verification techniques are introduced to enhance the completeness of the verification. Finally, the simulation result shows that this verification platform, which will improve the verification completeness and efficiency effectively, has the advantages of automation,random-test,and high-level reusability, integratabi lity.