The Research And Design Of Low-voltage LDMOS Device And High-voltage New Structure

With the development of power electronic technology,more and more attention was paid to power semiconductor devices.Power MOSFET,as an important branch of power semiconductor devices,rapidly occupies a large part of market share due to its advantages of fast switching speed,high input impedance,high operating frequency and simple driving circuit.Lateral Double Diffused MOSFET?LDMOS?structure was widely used in smart power ICs and high-voltage power ICs because its process is compatible to conditional CMOS process and it is easy to integrate.In power LDMOS device design process,in order to alleviate the contradiction between breakdown voltage and on-resistance,several common junction termination technologies were introduced,and reduce surface field technology?RESURF?and reduce bulk field technology?REBULF?were analyzed in detail,on this basis,the simulation of low-voltage and high-voltage LDMOS devices were designed and optimized,respectively.In automotive electronics,smart home and other applications,the low-voltage LDMOS device,as the core of circute,determines the performance of the entire circuit,so the design of low-voltage LDMOS device is essential.A 60V low-voltage LDMOS device was designed and optimized in this paper,then its process flow was introduced in detail,finally the breakdown mechanism of the device is analyzed,and on this basis,the key parameters were found that will affect the electrical performance of the device seriously.Different simulation experiments were designed for these parameters,finally a set of optimal parameters were found,and the threshold voltage of this LDMOS device is 1.7V,the breakdown voltage is 106.4V,the on-resistance is 4.7m?·cm^-2.Although low-voltage LDMOS devices were widely used,designing LDMOS devices with high breakdown voltage and low on-resistance is still one of the important research directions.However,due to the restriction of isolation technology in process flow,the usual high-voltage LDMOS requires thin epitaxial layers.Therefore,the longitudinal breakdown voltage is almost entirely borne by the substrate,so the breakdown voltage of the device can be effectively improved by raising the substrate breakdown voltage.Based on this idea,a novel LDMOS structure with N-type floating island was proposed in this paper.This structure is different from the conventional LDMOS structure in that multiple N-type floating islands were introduced into the substrate depletion layer under the drain.These N-type floating islands expand the depletion region boundary in the substrate layer lowering the high electric field underneath drain area and import several new peak values in vertical direction which make the lateral and vertical electric field optimized and the breakdown voltage significantly improved.The final simulation results of this high-voltage LDMOS device show that the breakdown voltage is 916.4V,the on-resistance is 0.436?·cm^-2 and the finger-of-merit is 1.926MW·cm^-2.