Reseach On The Breakdown Mechanism Of Thin Layer SOI PLDMOS

Silicon on insulator(SOI) technology is more and more widely used in power integrated circuits for its advantage over junction isolation technology, such as high speed, high integration level, low leakage current and superior isolation. Thin layer SOI is commonly applied to high voltage driver circuits since it has better performance in latch-up suppression, kink effect elimination, parasitic effect decay. p LDMOS is a common high-side device in high voltage level shift circuits. The buried oxide layer of thin layer SOI pLDMOS can’t be too thick for the consideration of better isolation and radiation, which limits the breakdown voltage(BV) of the device. What’s more, high-side SOI p LDMOS doesn’t meet the RESURF condition in the application, increasing the difficulty of design. To solve these problems, the breakdown mechanism of 300 V thin layer SOI LVD pLDMOS and 200 V thin layer SOI pLDMOS is researched and the corresponding integrated process is developed. The main research contents are below:1. 300 V thin layer SOI LVD pLDMOSThe breakdown characteristics of SOI p LDMOS is improved by inducing the lateral variation doping technology(LVD) and double RESURF and the SOI pLDMOS used in 300 V level shift circuit is developed. Simulation design method of SOI pLDMOS in fixed power apply application is proposed and compared with the conventional simulation method. The actual application of the device can be better reflected with the proposed simulation method. Through the combination simulation of process and device, the BV of thin layer SOI LVD pLDMOS reaches 594 V based on 3μm-thick buried oxide layer and 1.5μm-thick top silicon layer SOI, meeting the circuit application requirement.2. 200 V thin layer SOI pLDMOSThe breakdown characteristics of SOI pLDMOS is improved by inducing multi-field plates and additional implantation technology and applied under the proposed simulation method. Multi-field plates technology can realize an uniform distribution of the surface electric field, avoiding early breakdown at surface. Shallow junction p-field is realized by additional implantation technology, solving the problem of the channel disconnection and eliminating punch-through breakdown of back-gate. The high and low voltage compatible process for the SOI pLDMOS is developed and experiment demonstrated. The experiment results show that the 200 V thin layer SOI pLDMOS obtain a BV of 330 V and is used in 200 V driver circuit which realizes level shift from 0~5V to 0~200V successfully.