Design And Implementation Of The High Precision And Large Dynamic Rang Delay System Based On FPGA

Delay system, which has the characteristics of high-precision and large dynamic range, is widely used in electronic systems. The research methods of delay system are diversified, divided into fiber delay, analog circuit delay, and digital circuit delay. Each delay method has its own advantages and disadvantages. It is difficult to meet high precision, large dynamic range, integration and other performance indicators at the same time. With the development of FPGA technology, a platform to design the delay system inside the device is provided. FPGA chip has many excellent characteristics, which is widely used in radar systems. If delay system and other signal processing modules are integrated in the chip, there will be a very important engineering significance.In this paper, we design a high precision and large dynamic rang delay system about signal considering the actual application. The main contents are as follows:1. Summarize the design methods of the delay circuit, obtain the design ideas about high precision and large dynamic delay circuit, which is divided into coarse delay and fine delay. Analyze the delay system of the FPGA. Summarize the various design methods about the coarse delay units and fine delay units. Establish a delay system program by comparing the various programs. Specifically, discuss the factors that affect the accuracy of the delay program.2. In the delay system design, the core technology is the design of phase locked loop, which has having a phase shift function of high accuracy. This paper analyzes the principles and structure of the PLL, describes the internal components embedded PLL, combed the relationship of the parameters in the scan chain, and highlights the PLL reconfiguration, and dynamic phase reconfiguration function.3. Combined with the engineering indicators, complete the overall design and implementation of the high precision and large dynamic rang delay system. The system includes the following sections: counter delay module, phase locked loop module with dynamic phase reconfiguration function, sampling module with the same frequency and different phase, chirp signal module, serial communication module. Illustrate the design principle and method of each module. Solve the problem of metastable when asynchronous sampling clock.4. Each module in the delay system in the delay system based on FPGA development board. Analyze the delay system accurately by using simulation software, especially for high precision delay section. Do multiple measurements by changing the amount of delay, analyze the delay time of the delay system, and summarize up the source of the errors. Verify the rationality and correctness of the design. The delay system meets the performance.