Scan Tree Design To Optimaze The Number Of TSVs And Leaf Nodes For 3D-ICs

With the unceasing development of three-dimensional integrated circuits (3D-ICs), test is an indispensable link in the process of customization of integrated circuits. The scan-based design is the most popular design for testability (DFT). Multiple scan chains reduced test application time compared with single scan chain, while test data volume is unchanged. So scan tree architecture is proposed to reduce test application time and test data volume. The test application time of scan chain design is decided by the length of the longest scan chain, and scan tree architecture can shorten its length such that the test application time and test data volume can be reduced.In the process of 3D-ICs scan tree design, on the one hand, the scan cells, which layout in different layer, connected by through silicon via (TSV). However, the TSV technology is under developing and manufacturing TSV is costly. On the other hand, the leaf nodes of scan tree should be connected to scan output ports, which determines the number of test pins and test response data volume. Therefore, in order to decrease the 3D-ICs test cost, based on the factors of the number of TSV and leaf nodes number, two kinds of 3D-ICs scan tree architecture are proposed in this paper:Firstly, this paper present a method of 3D-ICs single scan tree architecture, which can optimize the number of TSV with the constraint of leaf nodes number. And build the model of 3D-ICs single scan tree with integer linear programming (ILP) algorithm to minimize the number of TSV with the condition of different leaf nodes number. Experimental results show the proposed method can effectively reduce the number of TSV compared to the existing method under the constraint of the same leaf nodes number.Secondly, relative to 3D-ICs single scan tree, multiple scan tree is proposed so as to reduce test application time further. The ILP model of 3D-ICs multiple scan tree is built based on the model of single scan tree. Moreover, respectively optimize the leaf nodes number under the constraint of the number of TSV. Experiments indicate the leaf nodes number for multiple scan tree is similar to single scan tree and the number of TSV increased manyfold, but the test application time greatly reduced.The proposed 3D-ICs single scan tree architecture effectively reduced the number of TSV and the 3D-ICs multiple scan tree architecture decreased the test application time and the leaf nodes number effectively.