A Response Compactor Based On Extended Compatibilities Scan Tree Construction

With the scale, complexity and density of integrated circuit growing in geometric progression; the test of an IC becomes more and more difficulty. Lots of problems occurred. For instance, the tradition testing methods can not assure the reliability of a system any more. There is an urgent need of some new theories and techniques to solve these problems. Therefore, some design for testability (DFT) techniques were proposed. Full scan testing, one of the most effective and popular design for test techniques, transforms the test generation problem of sequence circuits into that of combination circuits. Full scan design reduces the complexity of test generation and increases the fault coverage. However, it increase test application time, test stimuli data volume and test power significantly.The test application time of full scan design depends on the length of the longest scan chain. Some scan tree techniques were proposed to reduce test stimuli data volume and test application time by reducing the length of the longest scan chain. Extended compatibilities scan tree technique uses NOT and XOR functions to extend the compatibilities of scan cells, which reduces the length of the longest scan chain efficiently. However, the number of its scan outputs increases, which makes the test response data volume huge.To overcome the shortcomings of the extended compatibilities scan tree technique, this thesis proposes a test response compactor for extended compatibilities scan tree. The proposed compactor only comprises an XOR network. Taking the advantages of extended compatibilities and structure information of the combinational part of a circuit under test, the compactor can solve the problem brought by the error diffusion effectively. Meanwhile, the proposed technique reduces the number of scan outputs with less hardware keeping high fault coverage.During the operation of scan shifting, too many transitions lead the power dissipation much higher than that of the circuit at normal operation. Scan chain disable technique has proposed to reduce test power. In this technique, at a time in the scan testing (including both scan shifting and capture cycles), only one scan chain is active. The average, peak and total test power is reduced significantly. However, in this method, the test application time might be long.To overcome the drawbacks of the method above, this thesis proposes an low power and low cost scan test scheme and a test generation method based on this scheme. The experiment results demonstrate that our proposed scheme and test generation method can reduce the average power, peak power and test application time effectively.