Studies On Low Test Response Data Volume For Extended Compatibilities Scan Tree Construction

Full scan-based design is one of the most popular DFT techniques and it is widely used in very large scale integration (VLSI) circuits or in system-on-chip (SOC) cores. This DFT technique enhances all flip-flops of a circuit to scan cells, and concatenates all scan cells to one or more scan chains. Its test application time depends on the length of the longest scan chain. Unfortunately, although full scan-based design reduces test generation complexity drastically and provides high fault coverage by transforming a sequential circuit to its combinational part in test mode, the test cost including test application time, test data volume and test power is quit high. Extended compatibilities scan tree technique reduces test application time and test power drastically during shifting-in the same test data to the compatible scan cells by employing NOT and XOR functions. However, both its test response data volume and its wire length are increased. The contributions of this thesis are as follows.Firstly, this thesis proposes a novel construction for extended compatibilities scan tree to reduce test response data volume and wire length. The proposed technique comprises three processes including regrouping scan cells, reordering the cliques of scan cells and overturning the scan tree for the original extended compatibilities scan tree. Experimental results show that our approach achieves lower test response data volume and shorter wire length while keeping almost the same test application time, test input data volume, test power and area overhead compared with the previous construction. For ISCAS'89 benchmark circuits, the test response data volume is reduced 30.16% at most, and the wire length is reduced 50.73% in average.Then, this thesis proposes a novel test response compactor for extended compatibilities scan tree construction based on an XOR-network to reduce the test pins and test response data volume and overcome the error bits diffuse problem at the same time. The proposed compactor consists of a diffusion control logic and an XOR-network. The diffusion control logic eliminates the error bits diffusion problem. Experimental results show that the proposed compactor brings 0 aliasing for ISCAS'89 benchmark circuits while the compaction ratio is up to 74X.