Research And Design Of High Performance Digital Signal Processor

On the background of National Defence Preliminary 95' projects, this dissertation prosecutes the design research of DSP chip core. A core is a verified circuit module, with the purpose of design reuse in a large system chip. The first mission of the dissertation is to design NDSP25 processor, which is fully compatible with the TI TMS320C25 DSP processor in instruction set and cycle timing. This dissertation accomplishes the design of NDSP25 Digital Signal Processor micro-architecture with the Top-Down high level design methodology, finishes the implementation of all components, as well as design-for-test. The second mission of the dissertation is to prosecute the design of superscalar DSP processor. As the C25 DSP processor was introduced more than one decade ago, the dissertation proposes the micro-architecture design of the superscalar DSP processor to improve the DSP core performance, covering the following design aspects of instruction multi-issue and implementation of superscalar pipeline schedule units. The research results of the dissertation are basal to the design of high performance DSP processor. The corresponding research work has not yet been reported previously.According to the research, the major work done is as following:1. With high-level design technique, via Top-Down design methodology, the dissertation accomplishes system micro-architecture design of NDSP25 DSP processor core, discusses the final implementation of all design components, and provides the gate level synthesis results. The FPGA based prototype system is verified successfully. The optimized design of pipeline control unit is also proposed, which greatly minimizes the FSM states from 85 down to 23, with improvement in circuit speed and area utilizing.2. The method of DFT (Design For Test) is used to increase the testability of the self-developed NDSP25 core, as there is no DFT design in C25 DSP processor. According to the test aim of NDSP25 core, the dissertation proposes the appropriate DFT design strategy, finishes the test structure design. At the cost of less than 3% of total core area, this DFT design achieves the fault coverage of89. 34% using a test instruction set of 2165 instructions.3. Detailed research on superscalar micro-architecture is presented, contributing to the following design of superscalar DSP processor micro-architecture. Based on the Design Space theory, the dissertation proposes the instruction issue policy of superscalar DSP processor: by the way of register renaming, dynamic branch prediction, gliding instruction window and in-order issue. This issue policy effectively solves the problem of false data dependency, improves the issue rate and minimizes the influence of control hazard.4. Based on the NDSP25 instruction set, it proposes the micro-architecture design of RISC-like SDSP suprescalar DSP processor. Compared with the scalar DSP processor, this new SDSP micro-architecture could achieve about 3 times general performance speedup.5. A modified dynamic Branch Target Buffer(BTB) unit is designed, with the focus on minimizing superscalar DSP processor wrong branch penalty. It can perform multiple branch predictions every cycle, at the same time it achieves branch prediction accuracy as high as 86. 6%.This research work is sponsored by National Defence Preliminary 95' projects entitled "Military MPU&MCU techniques", "System Behavioral Level 1C CAD and Library Development". The research results of the dissertation will be contributive to the design process of the self-developed DSP processor of our own nation, and have profound application futures.